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Jason Poovey

Researcher in Data Analytics and Computer Architecture; High Performance Computing Developer

 I am a researcher and developer focusing on solving the challenges in data analytics applications on massive data with a focus on live streaming data. My expertise includes graph analytics, computer architecture, and high performance algorithms.

 My Interests and Expertise

My expertise spans from designing novel computer architectures to developing high performance backend algorithms to developing usable web tools to interact with and analyze data. I have been an active developer of STINGER, an open-source graph platform for analysis of massive streaming graphs. My prior work has focused on solving problems ranging from multi-level cache coherency, novel memory architectures, workload characterization, streaming data analytics, graph algorithms, processing near memory, and social media analysis.


Ph.D. (in progress) in Computer Science

ABDGeorgia Institute of Technology

M.S. in Computer Engineering

2007-2009North Carolina State University

B.S. in Computer Engineering

2003-2007North Carolina State University

B.S. in Electrical Engineering

2003-2007North Carolina State University

Academic Awards

Engineering Dean's Scholarship

Dean's Fellowship

GSA University Wide
Outstanding Teaching Assistant

Invited Talks/Conference Presentations

NASA Langley

Big Data Analytics Seminar2014


2012Presented work on accelerating cycle accurate simulation of parallel workloads


2011Presented work on detecting parallel patterns of workloads using architectural characteristics

Public Grants/Contracts


2013-2014DARPA seedling to study processing in memory controller (PIMC) techniques for accelerating data-irregular workloads such as large graphs


Research Scientist II

10/2012 - PresentGeorgia Tech Research Institute

Researcher in the Information and Communication Lab in the Innovative Computing Division. Research Focus has been on research in big data analytics, parallel computing, and application specific novel architecture design. Also play an active role in business development, briefing potential customers and writing proposals and white papers. Technical lead of the graph analytics component of the BlackForest application that uses STINGER.

Software Developer

athenahealth03/2012 - 10/2012

Developer on the Advanced Reporting team writing Perl code and SQL queries to enhance the reporting infrastructure within AthenaNet

Graduate Research Assistant

05/2009 - 03/2012Georgia Tech College of Computing

Research focus was on Parallel Pattern Detection to inform micro-architectural improvements and perform workload characterization. Also worked with other researchers on scalable cache coherence, efficient cycle accurate simulation techniques, and novel memory architectures.

Graduate Intern

Summer 2008Intel Corp.

Developed an assembler from scratch for the Ct project; Defined the assembly language and interfaced with existing tools for Ct/Larabee (now released as the Intel Phi).

Research Assistant

2006 - 2009NC State Computer Engineering Department

Worked on a project to characterize an embedded benchmark suite (EEMBC); Worked in a team of graduate students assisting with publications and research in the field of computer architecture. Projects focused on opcode minimization techniques for a configurable architecture and on complex hardware prefetchers.

Skills and Expertise



Parallel Programming (OpenMP, MPI, Pthreads, TBB)










Flex and Bison

Technical Writing

Graph Algorithms

Data Analytics

Teaching Expertise

Computer Architecture - beginning to doctoral level

Introductory Programming - any high level language or assembly

Advanced Programming - C, C++, Python, Parallel Programming

Simulation and Modeling

Compiler Design/Optimization

Teaching Experience

Georgia Institute of Technology

2015Adjunct Lecturer – “ECE6101: Advanced Parallel and Distributed Computer Architecture”

Lead instructor of the second-level graduate course in computer architecture. Topics discussed include microarchitecture design of shared memory multiprocessors ranging from buses and directories; cache coherence protocol design and verification; parallel programming with OpenMP; transactional memory; and GPGPU architectures.

Emory University

2014Adjunct Lecturer – “CS170: Introduction to Computer Science”

Lead instructor of freshman level Computer Science course based in Java

Georgia Institute of Technology

2012-2013Teaching Assistant/Lecturer – “CS6290: High Performance Computer Architecture”

Graduate Level course in Computer Architecture

North Carolina State University

2006-2009Adjunct Lecturer/Head Teaching Assistant – “ECE 109: Introduction to Computing Systems”

Freshman level course in Computer Architecture. Covers material from binary, logic gates, transistors, and basic assembly.


  1. D. Appling, E. Briscoe, D. Ediger, J. Poovey, R. McColl “Deriving Disaster-Related Information from Social Media.” KDD-LESI 2014
  2. D. Ediger, D. Appling, E. Briscoe, R. McColl, J. Poovey “Real-Time Streaming Intelligence: Integrating Graph and NLP Analytics.” HPEC, 2014
  3. R. McColl, D. Ediger, J. Poovey, D. Campbell, and D.A. Bader “A Brief Study of Open Source Graph Databases,” ArXiv e-prints. cs.DB 1309.2675. September, 2013.
  4. J. G. Beu, J.A. Poovey, E.R. Hein, T.M. Conte, “High-Speed Formal Verification of Heterogeneous Coherence Hierarchies,” HPCA 2013.
  5. P. D. Bryan, J. A. Poovey, J. G. Beu and T. M. Conte, “Accelerating Multi-threaded Application Simulation Through Barrier-Interval Time- Parallelism,” Proceedings of the IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS'12), (Washington, D.C), Aug., 2012.
  6. R. A. Bheda, J. A. Poovey, J. G. Beu and T.M. Conte, "Energy Efficient Phase Change Memory Based Main Memory for Future High Performance Systems," Proceedings of the 2nd International Green Computing Conference (IGCC'11), Orlando, Florida, July 25-28, 2011.
  7. J. A. Poovey, B. P. Railing and T. M. Conte, “Parallel pattern detection for architectural improvements,” Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism (HotPar), (Berkeley, CA), May 26–27, 2011.
  8. Jason A. Poovey, Thomas M. Conte, Markus Levy, Shay Gal-On, "A Benchmark Characterization of the EEMBC Benchmark Suite," IEEE Micro, pp. 18-29, September/October, 2009
  9. Balaji V. Iyer, Jason A. Poovey and Thomas M. Conte, "Energy-Aware Opcode Design," 23rd International Conference on Computer Design, Lake Tahoe, CA, 2008
  10. Jason A. Poovey, “Characterization of the EEMBC Benchmark Suite,” Technical Report, EEMBC, 2007. Published on EEMBC website at


Personal Information

Office Address 75 5th St. NW


 GA, 30318

Contact Me

Office 404.407.7450

Cell 704.576.1598

jason.poovey (at) Email


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