My expertise spans from designing novel computer architectures to developing high performance backend algorithms to developing usable web tools to interact with and analyze data. I have been an active developer of STINGER, an open-source graph platform for analysis of massive streaming graphs. My prior work has focused on solving problems ranging from multi-level cache coherency, novel memory architectures, workload characterization, streaming data analytics, graph algorithms, processing near memory, and social media analysis.
Researcher in the Information and Communication Lab in the Innovative Computing Division. Research Focus has been on research in big data analytics, parallel computing, and application specific novel architecture design. Also play an active role in business development, briefing potential customers and writing proposals and white papers. Technical lead of the graph analytics component of the BlackForest application that uses STINGER.
Developer on the Advanced Reporting team writing Perl code and SQL queries to enhance the reporting infrastructure within AthenaNet
Research focus was on Parallel Pattern Detection to inform micro-architectural improvements and perform workload characterization. Also worked with other researchers on scalable cache coherence, efficient cycle accurate simulation techniques, and novel memory architectures.
Developed an assembler from scratch for the Ct project; Defined the assembly language and interfaced with existing tools for Ct/Larabee (now released as the Intel Phi).
Worked on a project to characterize an embedded benchmark suite (EEMBC); Worked in a team of graduate students assisting with publications and research in the field of computer architecture. Projects focused on opcode minimization techniques for a configurable architecture and on complex hardware prefetchers.
Lead instructor of the second-level graduate course in computer architecture. Topics discussed include microarchitecture design of shared memory multiprocessors ranging from buses and directories; cache coherence protocol design and verification; parallel programming with OpenMP; transactional memory; and GPGPU architectures.
Lead instructor of freshman level Computer Science course based in Java
Graduate Level course in Computer Architecture
Freshman level course in Computer Architecture. Covers material from binary, logic gates, transistors, and basic assembly.